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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Parallel Thread Execution</span></span>
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<p><b>Parallel Thread Execution</b> (<b>PTX</b> or <b>NVPTX</b><sup id="cite_ref-:0_1-0" class="reference"><a href="#cite_note-:0-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup>) is a low-level <a href="Parallel_computing" title="Parallel computing">parallel</a> <a href="Thread_(computing)" title="Thread (computing)">thread</a> <a href="Execution_(computing)" title="Execution (computing)">execution</a> <a href="Virtual_machine" title="Virtual machine">virtual machine</a> and <a href="Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> used in <a href="Nvidia" title="Nvidia">Nvidia</a>'s Compute Unified Device Architecture (<a href="CUDA" title="CUDA">CUDA</a>) programming environment. The <a href="Nvidia_CUDA_Compiler" title="Nvidia CUDA Compiler">Nvidia CUDA Compiler</a> (NVCC) translates code written in CUDA, a <a href="C%2B%2B" title="C++">C++</a>-like language, into PTX instructions (an <a href="Intermediate_language" class="mw-redirect" title="Intermediate language">IL</a>), and the graphics driver contains a <a href="Compiler" title="Compiler">compiler</a> which translates PTX instructions into executable binary code,<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> which can run on the processing cores of <a href="List_of_Nvidia_graphics_processing_units" title="List of Nvidia graphics processing units">Nvidia</a> <a href="Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPUs). The <a href="GNU_Compiler_Collection" title="GNU Compiler Collection">GNU Compiler Collection</a><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> and <a href="LLVM" title="LLVM">LLVM</a><sup id="cite_ref-:0_1-1" class="reference"><a href="#cite_note-:0-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> also have the ability to generate PTX. Inline PTX assembly can be used in CUDA.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>
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<div class="mw-heading mw-heading2"><h2 id="Registers">Registers</h2></div>
<p>PTX uses an arbitrarily large <a href="Processor_register" title="Processor register">processor register</a> set; the output from the compiler is almost pure <a href="Static_single-assignment_form" title="Static single-assignment form">static single-assignment form</a>, with consecutive lines generally referring to consecutive registers. Programs start with declarations of the form
</p>
<div class="mw-highlight mw-highlight-lang-ptx mw-content-ltr" dir="ltr"><pre><span class="kr">.reg</span><span class="w"> </span><span class="kt">.u32</span><span class="w"> </span><span class="nv">%r</span><span class="p"><</span><span class="m">335</span><span class="p">>;</span><span class="w"> </span><span class="c">// declare 335 registers %r0, %r1, ..., %r334 of type unsigned 32-bit integer</span>
</pre></div>
<p>It is a three-argument assembly language, and almost all instructions explicitly list the data type (in sign and width) on which they operate. Register names are preceded with a % character and constants are literal, e.g.:
</p>
<div class="mw-highlight mw-highlight-lang-ptx mw-content-ltr" dir="ltr"><pre><span class="k">shr</span><span class="kt">.u64</span><span class="w"> </span><span class="nv">%rd14</span><span class="o">,</span><span class="w"> </span><span class="nv">%rd12</span><span class="o">,</span><span class="w"> </span><span class="m">32</span><span class="p">;</span><span class="w"> </span><span class="c">// shift right an unsigned 64-bit integer from %rd12 by 32 positions, result in %rd14</span>
<span class="k">cvt</span><span class="kt">.u64.u32</span><span class="w"> </span><span class="nv">%rd142</span><span class="o">,</span><span class="w"> </span><span class="nv">%r112</span><span class="p">;</span><span class="w"> </span><span class="c">// convert an unsigned 32-bit integer to 64-bit</span>
</pre></div>
<p>There are predicate registers, but compiled code in shader model 1.0 uses these only in conjunction with branch commands; the conditional branch is
</p>
<div class="mw-highlight mw-highlight-lang-ptx mw-content-ltr" dir="ltr"><pre><span class="err">@</span><span class="nv">%p14</span><span class="w"> </span><span class="k">bra</span><span class="w"> </span><span class="nv">$label</span><span class="p">;</span><span class="w"> </span><span class="c">// branch to $label</span>
</pre></div>
<p>The <code>setp.cc.type</code> instruction sets a predicate register to the result of comparing two registers of appropriate type, there is also a <code>set</code> instruction, where <code class="mw-highlight mw-highlight-lang-ptx mw-content-ltr" dir="ltr"><span class="k">set</span><span class="nv">.le.u32.u64</span><span class="w"> </span><span class="nv">%r101</span><span class="o">,</span><span class="w"> </span><span class="nv">%rd12</span><span class="o">,</span><span class="w"> </span><span class="nv">%rd28</span></code> sets the 32-bit register <code>%r101</code> to <code>0xffffffff</code> if the 64-bit register <code>%rd12</code> is less than or equal to the 64-bit register <code>%rd28</code>. Otherwise <code>%r101</code> is set to <code>0x00000000</code>.
</p><p>There are a few predefined identifiers that denote pseudoregisters. Among others, <code>%tid, %ntid, %ctaid</code>, and <code>%nctaid</code> contain, respectively, thread indices, block dimensions, block indices, and grid dimensions.<sup id="cite_ref-ptx-isa_5-0" class="reference"><a href="#cite_note-ptx-isa-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="State_spaces">State spaces</h2></div>
<p>Load (<code>ld</code>) and store (<code>st</code>) commands refer to one of several distinct state spaces (memory banks), e.g. <code>ld.param</code>.
There are eight state spaces:<sup id="cite_ref-ptx-isa_5-1" class="reference"><a href="#cite_note-ptx-isa-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>
</p>
<dl><dt><code>.reg</code></dt>
<dd>registers</dd>
<dt><code>.sreg</code></dt>
<dd>special, read-only, platform-specific registers</dd>
<dt><code>.const</code></dt>
<dd>shared, read-only memory</dd>
<dt><code>.global</code></dt>
<dd>global memory, shared by all threads</dd>
<dt><code>.local</code></dt>
<dd>local memory, private to each thread</dd>
<dt><code>.param</code></dt>
<dd>parameters passed to the kernel</dd>
<dt><code>.shared</code></dt>
<dd>memory shared between threads in a block</dd>
<dt><code>.tex</code></dt>
<dd>global texture memory (deprecated)</dd></dl>
<p>Shared memory is declared in the PTX file via lines at the start of the form:
</p>
<div class="mw-highlight mw-highlight-lang-ptx mw-content-ltr" dir="ltr"><pre><span class="kp">.shared</span><span class="w"> </span><span class="kr">.align</span><span class="w"> </span><span class="m">8</span><span class="w"> </span><span class="kt">.b8</span><span class="w"> </span><span class="nv">pbatch_cache</span><span class="p">[</span><span class="m">15744</span><span class="p">];</span><span class="w"> </span><span class="c">// define 15,744 bytes, aligned to an 8-byte boundary</span>
</pre></div>
<p>Writing kernels in PTX requires explicitly registering PTX modules via the CUDA Driver API, typically more cumbersome than using the CUDA Runtime API and Nvidia's CUDA compiler, nvcc. The GPU Ocelot project provided an API to register PTX modules alongside CUDA Runtime API kernel invocations, though the GPU Ocelot is no longer actively maintained.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>
</p>
<div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2></div>
<ul><li><a href="Standard_Portable_Intermediate_Representation" title="Standard Portable Intermediate Representation">Standard Portable Intermediate Representation</a> (SPIR)</li>
<li><a href="CUDA_binary" class="mw-redirect" title="CUDA binary">CUDA binary</a> (cubin) – a type of fat binary</li></ul>
<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>
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</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://llvm.org/docs/NVPTXUsage.html">"User Guide for NVPTX Back-end – LLVM 7 documentation"</a>. <i>llvm.org</i>.</cite></span>
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<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://docs.nvidia.com/cuda/inline-ptx-assembly/index.html">"Inline PTX Assembly in CUDA"</a>. <i>docs.nvidia.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-11-03</span></span>.</cite></span>
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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>
<ul><li><a rel="nofollow" class="external text" href="https://docs.nvidia.com/cuda/parallel-thread-execution/">PTX ISA page on NVIDIA Developer Zone</a></li></ul></div><!--htdig_noindex--><div><div class="zim-footer">
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